Some computing systems implement translation software to translate portions of target instruction set architecture (ISA) instructions into native instructions that may be executed more quickly and efficiently through various optimization techniques such as combining, reorganizing, and eliminating instructions. More particularly, in transactional computing systems that have the capability to speculate and rollback operations, translations may be optimized in ways that potentially violate the semantics of the target ISA. Due to such optimizations, once a translation has been generated, it can be difficult to distinguish whether events (e.g., architectural fault such as a page violation) encountered while executing a translation are architecturally valid or are spuriously created by over-optimization of the translation.